1. Field of Invention
The present invention relates to a method for fabricating a semiconductor device substrate. More particularly, the present invention relates to a method for fabricating a high-voltage device substrate capable of preventing junction breakdown and leakage current in the source/drain regions of a MOS transistor.
2. Description of Related Art
In general, most high-voltage MOS devices utilize the thickening of an isolating layer between the gate and the source/drain regions as a means of lowering the horizontal electric field within the channel. Alternatively, the drift regions below the isolation layer and the graded regions beneath the source/drain regions are lightly doped to provide the necessary voltage gradient. The two above measures are capable of increasing junction breakdown voltage in the source/drain regions so that the MOS transistor is able to operate normally despite the application of a high voltage.
As the level of integration for semiconductor devices continues to increase, rules for forming high-voltage devices become more stringent. Besides having to increase the degree of integration, the distance of separation between two neighboring devices has to be carefully planned. The most commonly used method for preparing a MOS device for high voltages is to increase the distance between neighboring devices and/or adding one more lightly doped layer to provide the necessary voltage gradient. Therefore, before a high-voltage device is formed, the substrate has to undergo a number of processing treatments to enhance its voltage bearing capacity. However, the difference in the height between substrate surfaces in different doped regions for a conventionally processed high-voltage MOS device substrate is small. Hence, when an epitaxial layer is grown on the substrate, the alignment of masks in subsequent processing operations is difficult.
To get a better understanding of the processing steps in fabricating a conventional high-voltage device substrate, the progression of manufacturing steps is illustrated using FIGS. 1A through 1K.
First, as shown in FIG. 1A, a substrate 100 such as a P-type substrate is provided. Then, a pad oxide layer 102 is formed over the substrate 100 using a thermal oxidation method. Thereafter, a chemical vapor deposition (CVD) method is used to form a silicon nitride layer 104 over the pad oxide layer 102.
Next, as shown in FIG. 1B, using photolithographic and etching techniques, the silicon nitride layer 104 and the pad oxide layer 102 are patterned to form a stacked layer 106. The stacked layer 106 is composed of a silicon nitride layer 104a and a pad oxide layer 102a.
Next, as shown in FIG. 1C, a field oxide (FOX) layer 112 is formed between two neighboring stack layers 106 by a thermal oxidation process such as wet oxidation.
Next, as shown in FIG. 1D, the silicon nitride layer 104a is removed using a wet etching method, for example. Subsequently, ions are implanted to form a heavily doped P.sup.+ region 108 in the substrate underneath the pad oxide layer 102a. For example, the implantation can be carried out using boron (B.sup.11) ions with an implantation energy level of about 70 KeV and a dosage level of about 2.0.times.10.sup.15 /cm.sup.2.
Next, as shown in FIG. 1E, the pad oxide layer 102a and the field oxide layer 112 are removed to expose the entire substrate surface 100. Thereafter, an atmospheric pressure chemical vapor deposition (APCVD) method is used to deposit an oxide layer 122 over the substrate 100. Preferably, the oxide layer 122 is formed using tetra-ethyl-ortho-silicate (TEOS) as a gaseous reactant in an APCVD process. Since TEOS oxide layer requires densification, the oxide layer 122 also needs to be densified. For example, densification is carried out using a temperature of about 1000.degree. C. for about 10 to 30 minutes. After the densification operation, the oxide layer 122 will contract a little making it somewhat denser.
Next, as shown in FIG. 1F, a patterned photoresist layer 110 is formed over the oxide layer 122. Subsequently, the oxide layer 122 is anisotropically etched using the photoresist layer 110 as a mask. Hence, an oxide layer 122a is formed and at the same time the substrate region 100 is exposed so that ions of opposite polarity to the ions already in the doped region 108 are ready to be implanted.
Next, as shown in FIG. 1G, another ion implantation is carried out to implant ions having polarity opposite to the heavily doped P.sup.+ region 108. In other words, N-type ions are implanted into the substrate 100 to form a heavily doped N.sup.+ region 118. For example, the implantation can be carried out using arsenic (As.sup.75) ions with an implantation energy level of about 100 KeV and a dosage level of about 4.0.times.10.sup.14 /cm.sup.2.
Next, as shown in FIG. 1H, the photoresist layer 110 is removed. Then, an APCVD method is used to deposit another oxide layer 132 over the substrate 100, covering the heavily doped N+ region 118 and the oxide layer 122a. Preferably, the oxide layer 132 having a thickness of about 3000 .ANG. is deposited using TEOS as the gaseous reactant in an APCVD process.
Next, as shown in FIG. 1I, oxidation and dopant drive-in operations are carried out simultaneously. The silicon substrate 100 is placed inside a reaction chamber having some moisture in the atmosphere, and then heated to initiate thermal oxidation. The heat also drives the ions, implanted earlier in the doped regions, deeper into the substrate. Since the heavily doped N.sup.+ region 118a is only covered by a very thin layer of oxide 132 above it, silicon within the heavily doped N.sup.+ region 118a is able to oxidize into silicon dioxide. Consequently, an oxide layer 142 is formed between the silicon substrate 100 and the oxide layer 132, where the oxide layer 142 includes the former oxide layer 122a as well.
Next, as shown in FIG. 1J, the oxide layer above the silicon substrate 100 is completely removed. Both oxide layers 132 and 142 are removed to expose the entire silicon substrate surface 100.
Finally, as shown in FIG. 1K, an epitaxial layer 150 is formed over the substrate surface 100 so that the fabrication of a silicon substrate suitable for forming high-voltage devices is complete. The epitaxial layer 150 can be formed using, for example, a chemical vapor deposition (CVD) method. The epitaxial layer 150, preferably having a thickness of about 19 .mu.m, can be turned into an N-type epitaxial layer if doping of N-type ions is also carried out during the CVD operation.
In the aforementioned fabrication process for a high-voltage device substrate, the difference in height level between the highest (in the P-doped region 108a) and lowest point (in the N-doped region 118a) on the substrate surface is small. Therefore, when the epitaxial layer 150 is formed over the substrate 100, the peak and the trough of the epitaxial layer will also be quite small. Consequently, when alignment marks are subsequently formed over the surface for alignment of photomasks in the fabrication of high-voltage devices, alignment will be inaccurate. This can lead to processing errors and an increase in product failure.
In light of the foregoing, there is a need to provide an improved method of fabricating high-voltage device substrate.